1. Field of the Invention
The invention relates to memory systems used in computers, and more particularly to memory systems using cache memory.
2. Discussion of the Related Art
Personal computer systems are becoming more powerful quite rapidly. Device manufacturers have been providing ever faster microprocessors for use in the computers. However, memory device speeds have not been increasing as fast as the microprocessors with which they are used. Fast memory devices are available, but their use as the main memory of the computer is generally prohibited because of their high cost.
One approach to solving the problem is to use a cache memory system. In a cache memory system a small amount of fast memory is used and slower, more cost effective memory is used as the main memory. Data contained in portions of the main memory is duplicated in the fast, cache memory so that when the necessary data is contained in the cache memory a fast operation can occur. A cache controller handles the task of determining if the desired information is contained in the cache memory and controlling the data transfer and the cache memory devices.
Intel Corporation (Intel) used the cache memory concept when developing the 80386 microprocessor family of devices. In addition to the 80386 microprocessor, an 82385 cache controller was developed. For detailed information on the devices please refer to handbooks provided by Intel, such as the Microprocessor and Peripheral Handbook, Volume 1. The 82385 is designed to directly control a 32 kbyte cache memory organized as either a direct mapped 8 k by 4 byte block or two 4 k by 4 byte blocks in a two way set associate configuration. In either format the 82385 assumes that the memory width, referred to in this case as the line size, is 4 bytes, a double word or dword.
However, a larger cache memory in many cases improves performance of the computer by improving the number of times the desired information is found to be in the cache, referred to as the hit rate. Thus the 32 kbyte limit imposed by the 82385 may have limited ultimate system performance.
The Model 70-A21 computer in the Personal System/2 line manufactured by International Business Machines Corporation (IBM) utilized the 82385 and yet had a 64 kbyte cache memory.
Intel provided an application note describing in general terms a method for using a 64 kbyte cache memory with the 82385. The basic approach required doubling the line size to 64 bits, a quadruple word or qword. Various address lines connected to the 82385 were shifted and external logic was required to perform a number of functions. The external logic had to drive one bit of the addressing to the cache memory to select the proper dword, this function no longer capable of being performed by the 82385, which only selected the proper qword. The external logic was required to control the write enables to the cache memory. The external logic had to monitor various lines to determine cache activity and when a miss occurred. The external logic had to capture and develop various cycle related signals such as Next Address (NA), Ready and Address Status (ADS).
During a cache read hit operation the external logic had only to complete the addressing of the cache memory. Similarly for a cache write hit, the external logic had only to complete the addressing. Cache write miss operations were unaffected as the cache memory was not involved.
Cache read miss operations were more complex. The external logic had the duty to provide the two dwords to the cache memory to fill the cache but had to make this operation appear as only a single operation to the 82385. When utilizing a 32 bit data bus, the external logic was required to drive the proper addresses onto the address bus, provide an additional ADS strobe and block any extra NA or READY signals to the 82385 to prevent it from proceeding. It was suggested that the dword undesired by the 80386 be obtained first and the dword desired by the 80386 obtained second.
Problems developed because the cache fill operation is not zero-based, that is, the least significant address bit could be one or zero, and yet the transfer had to be completed correctly. Additionally, the cache fill had to be done quickly or the fill time increase would offset any hit rate increases and could actually degrade system performance. A 64 bit wide memory path could be utilized between the cache memory and the main memory, but this would requiring 64 data lines which uses valuable circuit board space and increases radio frequency emissions to levels requiring expensive solutions to meet desired levels.
An alternative to using a cache memory system to increase cost effective system performance was to use a paged memory. Certain dynamic random access memory (DRAM) devices were available which allowed faster access under certain conditions. Conventionally in a DRAM the address inputs are multiplexed to reduce the physical size of the device page. One half of the address values were provided, called the row address, and then the remaining address values are provided, the column address. Thus, to obtain data both the row and the column addresses had to be provided and set up inside the device. However, in paged mode device, if the row address did not change, a page hit condition, only a new column address had to be provided, thus allowing the data transfer to occur quickly. However, if the row address changed, a page miss condition, the full cycle had to be performed. Thus, paged mode devices could be used to improve the performance of the computer without the burden of a complex cache system. The Compaq 386 manufactured by Compaq Computer Corporation used paged memory techniques.